International Conference on Innovations In Intelligent Instrumentation, Optimization And Signal Processing “ICIIIOSP-2013” 1 A Novel Approach for Multi-Bit Error Correction in Memories

Due to advance technologies transistor size shrinks which makes the devices more vulnerable to noise and radiation effect. This affects the reliability of memories. Built-in current sensors (BICS) have been success in the case of single event upset (SEC). The process is taken one step further by proposing specific error correction codes to protect memories against multiple-bit upsets and to improve yield have been proposed. The method is evaluated using fault injection experiments. The results are compared with Hamming codes. The proposed codes provide a better performance compared to that of the hamming codes in terms of Single Event Upset. In the case of the Multi Bit Upset it provides better coverage in error deduction and correction